Chirevo chekuvanzika: Kuvanzika kwako kwakakosha kwazvo kwatiri
Muenzaniso Nha.: NSO4GU3AB
Kutakura: Ocean,Air,Express,Land
Mutero Wechibharo: L/C,T/T,D/A
Incoterm: FOB,EXW,CIF
4GB 1600mhz 240-Pin DDR3 Udimm
Yakateverwa Nhoroondo
Revision No. |
History |
Draft Date |
Remark |
1.0 |
Initial Release |
Apr. 2022 |
|
Kuraira tafura yeruzivo
Model |
Density |
Speed |
Organization |
Component Composition |
NS04GU3AB |
4GB |
1600MHz |
512Mx64bit |
DDR3 256Mx8 *16 |
Tsanangudzo
Hengstar isina kubviswa DDR3 SDRAM Dimms (isina-mbiri data data syncchoronous dram NS04B ndeye 512m x 64-bit maviri rank Ddr3-1600 CL11 1.5V SDRAM Iyo SPD yakarongedzwa kuJede Steattle Latency Ddr3-1600 nguva ye 11-11-11 pa 1.5V. Imwe neimwe-pini-pini dimm inoshandisa goridhe yekubata minwe. Iyo SDRAM haina kuitirwa simm inoitirwa kushandiswa seyekukosha ndangariro kana yakaiswa mumasisitimu akadai sePC uye nzvimbo dzekushanda.
Zvimiro
power kugovera: vdd = 1.5V (1.25V kusvika 1.575V)
vddq = 1.5V (1.25V kusvika 1.575V)
800MHZ FCK ye 1600MB / sec / Pin
8 Yakazvimirira yemukati Bank
PRabhigragamable Cals Latency: 11, 10, 9, 8, 7, 6
PRogrammable Advertitive Latency: 0, CL - 2, kana CL - 1 Clock
8-Bit Pre-Fetch
Boburst Kureba:
bi-kutungamira kusiyanisa data dura strobe
Taura (pachako) calibration; Yemukati yekuzvisarudzira kuburikidza neZQ Pin (Rzq: 240 OHM ± 1%)
Žon kufa kubviswa uchishandisa ODT PIN
avarage Refresh Nguva 7.8us yakadzika pane tcase 85 ° C, 3.9us at 85 ° C <tase <95 ° C
asynchronous reset
ADADUKA YAKABUDA DATA-BUDAPT Drive Simba
Fly-ne topology
PCB: kureba 1.18 "(30mm)
Rohs inoenderana uye halogen-yemahara
Key Timing parameter
MT/s |
tRCD(ns) |
tRP(ns) |
tRC(ns) |
CL-tRCD-tRP |
DDR3-1600 |
13.125 |
13.125 |
48.125 |
2011/11/11 |
Kero tafura
Configuration |
Refresh count |
Row address |
Device bank address |
Device configuration |
Column Address |
Module rank address |
4GB |
8K |
32K A[14:0] |
8 BA[2:0] |
2Gb (256 Meg x 8) |
1K A[9:0] |
2 S#[1:0] |
PIN tsanangudzo
Symbol |
Type |
Description |
Ax |
Input |
Address inputs: Provide the row address for ACTIVE commands, and the column |
BAx |
Input |
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or |
CKx, |
Input |
Clock: Differential clock inputs. All control, command, and address input signals are |
CKEx |
Input |
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry |
DMx |
Input |
Data mask (x8 devices only): DM is an input mask signal for write data. Input data is |
ODTx |
Input |
On-die termination: Enables (registered HIGH) and disables (registered LOW) |
Par_In |
Input |
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. |
RAS#, |
Input |
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being |
RESET# |
Input |
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and |
Sx# |
Input |
Chip select: Enables (registered LOW) and disables (registered HIGH) the command |
SAx |
Input |
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address |
SCL |
Input |
Serial |
CBx |
I/O |
Check bits: Used for system error detection and correction. |
DQx |
I/O |
Data input/output: Bidirectional data bus. |
DQSx, |
I/O |
Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; |
SDA |
I/O |
Serial |
TDQSx, |
Output |
Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD |
Err_Out# |
Output (open |
Parity error output: Parity error found on the command and address bus. |
EVENT# |
Output (open |
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical |
VDD |
Supply |
Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The |
VDDSPD |
Supply |
Temperature sensor/SPD EEPROM power supply: 3.0–3.6V. |
VREFCA |
Supply |
Reference voltage: Control, command, and address VDD/2. |
VREFDQ |
Supply |
Reference voltage: DQ, DM VDD/2. |
VSS |
Supply |
Ground. |
VTT |
Supply |
Termination voltage: Used for control, command, and address VDD/2. |
NC |
– |
No connect: These pins are not connected on the module. |
NF |
– |
No function: These pins are connected within the module, but provide no functionality. |
Zvinyorwa : Iyo PIN Rondedzero tafura iri pazasi rondedzero yakazara yezvese zvinogoneka mapini kune ese DDR3 modules. Pini yese yakanyorwa may usatsigirwa pane iyi module. Ona mapini ekupa ruzivo ruzivo rwakananga kune iyi module.
Inoshanda Block Diagram
4GB, 512MX64 module (2rank ye x8)
Module zviyero
Front Fort
Front Fort
Zvinyorwa:
1.Zvirimo zviyero zviri mumamirimita (inches); Max / min kana kujairika (type) kwawakacherechedzwa.
2.Nealance pane zvese zviyero ± 0.15mm kunze kwekunge zvataurwa neimwe nzira.
3.The Dimensional Diagram ndeyekunongedzera chete.
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